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74LVT16646 * 74LVTH16646 Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs
January 2000 Revised October 2001
74LVT16646 * 74LVTH16646 Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs
General Description
The LVT16646 and LVTH16646 contains sixteen noninverting bidirectional registered bus transceivers providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Each byte has separate control inputs which can be shorted together for full 16-bit operation. The DIR inputs determine the direction of data flow through the device. The CPAB and CPBA inputs load data into the registers on the LOW-to-HIGH transition (see Functional Description). The LVTH16646 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These transceivers are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT16646 and LVTH16646 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation.
Features
s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH16646) s Also available without bushold feature (74LVT16646) s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink -32 mA/+64 mA s Latch-up conforms to JEDEC JED78 s ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V
Ordering Code:
Order Number 74LVT16646MEA (Preliminary) 74LVT16646MTD (Preliminary) 74LVTH16646MEA 74LVTH16646MTD Package Number MS56A MTD56 MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
(c) 2001 Fairchild Semiconductor Corporation
DS012023
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74LVT16646 * 74LVTH16646
Connection Diagram Pin Descriptions
Pin Names A0-A15 B0-B15 CPABn, CPBAn SABn, SBAn OE1, OE2 DIRn Description Data Register A Inputs/3-STATE Outputs Data Register B Inputs/3-STATE Outputs Clock Pulse Inputs Select Inputs Output Enable Inputs Direction Control Inputs
Truth Table
(Note 1) Inputs OE1 H H H L L L L L L L L DIR1 X X X H H H H L L L L CPAB1 CPBA1 SAB1 H or L X SBA1 X X X X X X X L L H H Output Input Input Input Input Data I/O A0-7 B0-7 Isolation Clock An Data into A Register Clock Bn Data Into B Register An to Bn--Real Time (Transparent Mode) Output Clock An Data to A Register A Register to Bn (Stored Mode) Clock An Data into A Register and Output to Bn Bn to An--Real Time (Transparent Mode) Clock Bn Data into B Register B Register to An (Stored Mode) Clock Bn into B Register and Output to An Output Operation Mode

X X X X X
H or L
X X X L L H H X X X X
X X X X X
H or L
H or L
H = HIGH Voltage Level X = Immaterial L = LOW Voltage Level = LOW-to-HIGH Transition.

X
Note 1: The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Also applies to data I/O (A and B: 8-15) and #2 control pins.
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74LVT16646 * 74LVTH16646
Functional Description
In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both. The select (SABn, SBAn) controls can multiplex stored and real-time. The examples shown below demonstrate the four fundamental bus-management functions that can be performed. The direction control (DIRn) determines which bus will receive data when OEn is LOW. In the isolation mode (OEn HIGH), A data may be stored in one register and/or B data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two busses, A or B, may be driven at a time.
Real-Time Transfer Bus B to Bus A
Real-Time Transfer Bus A to Bus B
OE DIR CPAB CPBA SAB SBA L L X X X L
OE DIR CPAB CPBA SAB SBA L H X X L X
Transfer Storage Data to A or B
Storage
OE DIR CPAB CPBA SAB SBA OE DIR CPAB CPBA SAB SBA L L L H X H or L H or L X X H H X L L H H H L X X X X L X X X X L X X X

X
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74LVT16646 * 74LVTH16646
Logic Diagrams
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74LVT16646 * 74LVTH16646
Absolute Maximum Ratings(Note 2)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 3) VI < GND VO < GND VO > VCC VO > VCC Output at HIGH State Output at LOW State V V mA mA mA mA mA
-0.5 to +4.6 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -50 -50
64 128
64 128 -65 to +150
C
Recommended Operating Conditions
Symbol VCC VI IOH IOL TA Supply Voltage Input Voltage HIGH-Level Output Current LOW-Level Output Current Free-Air Operating Temperature Input Edge Rate, VIN = 0.8V-2.0V, VCC = 3.0V Parameter Min 2.7 0 Max 3.6 5.5 Units V V mA
-32
64
-40
0
85 10
C
ns/V
t/V
Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 3: IO Absolute Maximum Rating must be observed.
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74LVT16646 * 74LVTH16646
DC Electrical Characteristics
Symbol VIK VIH VIL VOH Parameter Input Clamp Diode Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage VCC (V) 2.7 2.7-3.6 2.7-3.6 2.7-3.6 2.7 3.0 VOL Output LOW Voltage 2.7 2.7 3.0 3.0 3.0 II(HOLD) (Note 4) II(OD) (Note 4) II Bushold Input Over-Drive Current to Change State Input Current Control Pins Data Pins IOFF IPU/PD Power Off Leakage Current Power Up/Down 3-STATE Output Current IOZL (Note 4) 3-STATE Output Leakage Current IOZL IOZH IOZH+ ICCH ICCL ICCZ ICCZ+ ICC 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current Power Supply Current Power Supply Current Power Supply Current Power Supply Current Increase in Power Supply Current (Note 7)
Note 4: Applies to bushold version only (74LVTH16646) Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
T A = -40C to +85C Min 2.0 0.8 VCC - 0.2 2.4 2.0 0.2 0.5 0.4 0.5 0.55 75 -75 500 -500 10 1 -5 1 100 100 -5 -5 5 5 10 0.19 5 0.19 0.19 0.2 Max -1.2
Units V V V V V V V V V V A A A A A A A A A A A A A A A mA mA mA mA mA
Conditions II = -18 mA VO 0.1V or VO VCC - 0.1V IOH = -100 A IOH = -8 mA IOH = -32 mA IOL = 100 A IOL = 24 mA IOL = 16 mA IOL = 32 mA IOL = 64 mA VI = 0.8V VI = 2.0V (Note 5) (Note 6) VI = 5.5V VI = 0V or VCC VI = 0V VI = VCC 0V VI or VO 5.5V VO = 0.5V to 3.0V VI = GND or VCC VO = 0.0V VO = 0.5V VO = 3.6V VO = 3.0V VCC < VO 5.5V Outputs HIGH Outputs LOW Outputs Disabled VCC VO 5.5V,Outputs Disabled One Input at VCC - 0.6V Other Inputs at VCC or GND
Bushold Input Minimum Drive
3.0 3.0 3.6 3.6 3.6 0 0-1.5V 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6
IOZH (Note 4) 3-STATE Output Leakage Current
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL VCC (V) 3.3 3.3
(Note 8)
TA = 25C Units V V Conditions CL = 50 pF, RL = 500 (Note 9) (Note 9)
Min
Typ 0.8 -0.8
Max
Note 8: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 9: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. Output under test held LOW.
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74LVT16646 * 74LVTH16646
AC Electrical Characteristics
TA = -40C to +85C Symbol Parameter CL = 50 pF, RL = 500 VCC = 3.3 0.3V Min fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ tW tS tH tOSHL tOSLH Maximum Clock Frequency Propagation Delay CPAB or CPBA to A or B Propagation Delay Data to A or B Propagation Delay SBA or SAB to A or B Output Enable Time OE to A or B Output Disable Time OE to A or B Output Enable Time DIR to A or B Output Disable Time DIR to A or B Pulse Duration Setup Time Hold Time CPAB or CPBA HIGH or LOW A or B before CPAB or CPBA, Data HIGH A or B before CPAB or CPBA, Data LOW A or B after CPAB or CPBA, Data HIGH A or B after CPAB or CPBA, Data LOW Output to Output Skew (Note 10) 150 1.3 1.3 1.0 1.0 1.0 1.0 1.0 1.0 2.0 2.0 1.0 1.0 1.5 1.5 3.3 1.2 2.0 0.5 0.5 1.0 1.0 5.4 5.2 4.4 4.6 4.6 4.8 4.7 5.1 5.6 5.4 4.9 5.4 6.4 5.4 Max VCC = 2.7V Min 150 1.3 1.3 1.0 1.0 1.0 1.0 1.0 1.0 2.0 2.0 1.0 1.0 1.5 1.5 3.3 1.5 2.8 0.0 0.5 1.0 1.0 5.9 5.8 4.7 5.1 5.4 5.6 5.4 6.0 6.1 6.1 5.4 6.4 7.1 5.9 Max MHz ns ns ns ns ns ns ns ns ns ns ns Units
Note 10: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance
Symbol CIN CI/O
(Note 11)
Parameter Conditions VCC = Open, VI = 0V or VCC VCC = 3.0V, VO = 0V or VCC Typical 4 8 Units pF pF
Input Capacitance Input/Output Capacitance
Note 11: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
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74LVT16646 * 74LVTH16646
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS56A
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74LVT16646 * 74LVTH16646 Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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